Strain Measurements in ULSI Devices

Modern CMOS devices have dimensions which are progressively shrinking down towards 0.1mm and electrical isolation to avoid such unwanted effects as 'latch-up' is becoming particularly important. A key strategy in this regard is the use of oxide-filled trenches to produce the required isolation.

However, the presence of different materials adjacent to the Si devices, including oxide and poly-Si above the conducting channel, can lead to deleterious strains in the body of the devices which can affect their performance. Therefore, it is of some importance to measure these strains and the programme STREAM, with Italian, French and German collaborators seeks to achieve this.

Our role at Sheffield focuses upon the application of the FEGTEM to carry out very small scale convergent beam electron diffraction (CBED) work using the 1nm electron probe available. In this way, CBED patterns are obtained from device regions parallel to and just below device gates in order to give strain information at these positions.

A typical partially-processed device (from ST Microelectronics) is shown in Fig. 1 and the horizontal white line indicates the depth at which CBED patterns have been obtained.

Figure 1: FEGTEM cross-section of partially-processed CMOS device showing region from which CBED patterns are obtained

The quality of these patterns has been improved by electron energy loss filtering as an alternative to conventional sample cooling, which can lead to ambiguity due to differential contraction of different regions of a sample. Figure 2 shows the improvement in pattern quality achievable by zero-loss electron energy filtering. The strain measurements obtained by analysing such patterns will be employed to improve the computer simulation of device characteristics.

Figure 2a: CBED patterns unfiltered

Figure 2b: CBED patterns zero loss filtered