Studies of SiGe/Si HMOS Transistors
With the need for ever higher speed complementary metal oxide semiconductor (CMOS) devices, strategies to exceed the performance offered by elemental Si are of increasing importance. One promising route forward involves the use of SiGe layers in the device active regions, either as the conducting channel (p-channel devices) or as misfitting layers to strain the active Si channel in tension (n-channel devices).
However, although potentially compatible with conventional Si processing, a substantial amount of process development is required. The 'SiGe/Si HMOS' collaboration between a number of UK universities and selected industrial companies is addressing the problems involved and our group is employing the FEGTEM to carry out advanced structural and elemental analyses of corresponding materials structures.
Many examples of processed and part processed devices have been examined and information relating to gate oxide thickness, silicide distribution, etching behaviour, etc has been obtained.
Of particular interest is high resolution energy-filtered imaging (EFI) which has been used to map the detailed Ge concentration profiles across SiGe alloy channels and has demonstrated asymmetries associated with Ge segregation during layer growth: the results have been correlated with a theoretical segregation model.
Furthermore, when such structures are oxidized, 'snow-ploughing' of Ge is observed to occur at the oxide/SiGe interface and this has been quantified by EFI measurements. These types of materials behaviour have a strong influence upon device properties and it is particularly importance that they be fully understood so that they can be taken correctly into account during theoretical device modelling.